how can i compile vhdl code in xilinx software?
and i have already made half_adder and or gate so how can i make full_adder directly?

Hi chandar, u r using multiple architecture for single entity , u have to use configaration,
here is the correct code for Full adder using half adder in structural modelling
-- half adder
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(a,b:in bit;
   sum,carry:out bit);
end ha;
architecture behav of ha is
begin
sum<= a xor b;
carry<=a and b;
end behav;

---vhdl code for 2 input or gate
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(a,b:in bit;
   y:out bit);
end or2;
architecture behav of or2 is
begin
y<= a or b;
end behav;


--compile the above vhdl codes then compile the below vhdl code
--Fulladder using half adders
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity fa is
port(a,b,cin:in bit;
   sum,cout:out bit);
end fa;
architecture  struct_fa of fa is
component ha
port(a,b:in bit;
   sum,carry:out bit);
end component;
component or2
port(a,b:in bit;
   y:out bit);
end component;
signal x,y,z:bit;
begin
ha1: ha port map (a,b,x,y);
ha2: ha port map (x,cin,sum,z);
or1: or2 port map (z,y,cout);
end struct_fa