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<-- Previous Next -- > TOPIC: Half adder using structural modeling
Posted by: chandarpriya     9/26/2006 1:13:14 PM     Category: VHDL
Questions posted: 14         Comments Posted: 9

hi friends,
here is the code.its not compiling.can anyone help me pls.....


library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(a,b:in bit;
    sum,carry:out bit);
end ha;
architecture behav of ha is
begin
sum<= a xor b;
carry<=a and b;
end behav;
architecture structural of ha is
begin
component xor2
port(x,y:in bit;z:out bit);
end component;
component and2
port(l,m:in bit;n:out bit);
end component;
begin
x1:xor2 port map(a,b,sum);
x2:and2 port map(a,b,carry);
end structural;

Posted by: jdpatel     3/6/2013 12:52:52 AM
Comments Posted:1       

how can i compile vhdl code in xilinx software?
and i have already made half_adder and or gate so how can i make full_adder directly?


Posted by: kaito     3/17/2011 1:24:41 AM
Comments Posted:1       

hi virupaksha, i tried already to use your correct code but i have 1 problem that is cannot auto load. How to solve it?


Posted by: virupaksha     9/27/2006 12:54:15 AM
Comments Posted:2       

Hi chandar, u r using multiple architecture for single entity , u have to use configaration,
here is the correct code for Full adder using half adder in structural modelling
-- half adder
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port(a,b:in bit;
   sum,carry:out bit);
end ha;
architecture behav of ha is
begin
sum<= a xor b;
carry<=a and b;
end behav;

---vhdl code for 2 input or gate
library ieee;
use ieee.std_logic_1164.all;
entity or2 is
port(a,b:in bit;
   y:out bit);
end or2;
architecture behav of or2 is
begin
y<= a or b;
end behav;


--compile the above vhdl codes then compile the below vhdl code
--Fulladder using half adders
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity fa is
port(a,b,cin:in bit;
   sum,cout:out bit);
end fa;
architecture  struct_fa of fa is
component ha
port(a,b:in bit;
   sum,carry:out bit);
end component;
component or2
port(a,b:in bit;
   y:out bit);
end component;
signal x,y,z:bit;
begin
ha1: ha port map (a,b,x,y);
ha2: ha port map (x,cin,sum,z);
or1: or2 port map (z,y,cout);
end struct_fa





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