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<-- Previous Next -- > TOPIC: write a VHDL code for 4 bit shift register.
Posted by: bobbysingh     11/14/2007 2:45:00 AM     Category: VHDL
Questions posted: 4         Comments Posted: 0
write a VHDL code for 4 bit shift register.

Posted by: raj302     6/26/2011 2:45:56 AM
Comments Posted:1       Questions Posted:1

thanks


Posted by: comfortzone     8/14/2008 12:59:39 AM
Comments Posted:1       

thanks it was really helpful


Posted by: $---Jay---$     11/14/2007 5:21:59 AM
Comments Posted:104       Questions Posted:1

a sample code, redesign it for 4 bit...

---------------------------------------------------

library ieee ;
use ieee.std_logic_1164.all;

---------------------------------------------------

entity shift_reg is
port( I: in std_logic;
clock: in std_logic;
shift: in std_logic;
Q: out std_logic
);
end shift_reg;

---------------------------------------------------

architecture behv of shift_reg is

   -- initialize the declared signal
   signal S: std_logic_vector(2 downto 0):="111";

begin
   
   process(I, clock, shift, S)
   begin

-- everything happens upon the clock changing
if clock'event and clock='1' then
   if shift = '1' then
S <= I & S(2 downto 1);
   end if;
end if;

   end process;

   -- concurrent assignment
   Q <= S(0);

end behv;

----------------------------------------------------




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